Like Article. Next What happens when we turn on computer? Recommended Articles. Article Contributed By :. Shubham Bansal Easy Normal Medium Hard Expert. Writing code in comment? Please use ide. Load Comments. Ask Question. Asked 11 years, 2 months ago. Active 8 years, 10 months ago. Viewed 19k times. Improve this question. Add a comment. Active Oldest Votes. My original answer is below, if you want to understand the comments. New Answer As you say, there are a variety of measures.
Original answer Different people can mean different things, because as you say there are several measures. Improve this answer. Nick Fortescue Nick Fortescue Can you please elaborate, what do you mean by "Language is sloppy"? Their meaning changes slightly depending on what you are describing. It isn't the terms that are ambiguous, it's the actual processor designs. The various widths were all optimized separately and thus only loosely related.
The rise of C has "encouraged" the data and address widths to be the same, but it wasn't always that way. The actual bus widths were often completely different from either. The bit count of CPU's is quite accurately described at Wikipedia, it's not as sloppy as you describe it Thanks for comments, hopefully the wording is better now. Show 1 more comment. There's a good explanation of this at Wikipedia : In computer architecture, bit integers, memory addresses, or other data units are those that are at most 32 bits 4 octets wide.
Now let's talk about OS. Instruction word length is partially internal, sometimes an instruction can be longer than the bus the CPU is connected to program memory in a von-Neumann design, there is just one address space for both program memory and working memory with stack, etc.
Internally, that opcode has a certain width. Most CPU's use microcode to decode that opcode, this microcode can handle a certain width the instruction can have. That is the instruction word width. I'm not talking about microcode instructions. A CPU instruction is decoded by the microcode. Now this CPU instruction has a maximum length. This length is defined by hardware design of the CPU, and its microcode. It took two cycles to perform a full width fetch or store, but this was invisible to the programmer abstracted out by the cache architecture except in terms of sustained memory access speed.
Marting: Yes, but keep in mind, the opcode can be longer than the bus line's width! Or do you mean only the maximum opcode size internally, i.
If so, does that maximum decoded size really matter to a programmer at all? Felt this needed a short explanation rather than 7 long, inaccurate ones. The definitions are marketing terms more than precise technical terms.
The was classed as an 8-bit processor, but had bit address registers, a bit address bus, and 8, 16,and bit instructions. The MIPS architecture had option for bit data and bit addresses or bits for both, but the early implementations only had bit busses. Marketing usually preferred the biggest number possible, unless targeting the extremely low cost embedded market.
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